1. Field of the Invention
The present invention relates to a silicon chip and a method for making the same, and more particularly to a silicon chip having a through via and a method for making the same.
2. Description of the Related Art
FIG. 1 shows a cross-sectional view of a conventional silicon chip having a through via, and FIG. 2 is a partial enlarged view of FIG. 1. The conventional silicon chip 1 having a through via has a silicon substrate 11, at least one electrical device 12, at least one through via 13, a passivation layer 14 and a redistribution layer 15. The silicon substrate 11 has a first surface 111, a second surface 112 and at least one through hole 113. The electrical device 12 is disposed in the silicon substrate 11, and exposed to the second surface 112 of the silicon substrate 11. The through via 13 penetrates the silicon substrate 11. The through via 13 comprises a barrier layer 133 and a conductor 134. The barrier layer 133 is disposed on the side wall of the through hole 113, and the conductor 134 is disposed in the barrier layer 133. The through via 13 has a first end 131 and a second end 132. The first end 131 is exposed to the first surface 111 of the silicon substrate 11, and the second end 132 connects the electrical device 12. The passivation layer 14 is disposed on the first surface 111 of the silicon substrate 11, and the passivation layer 14 has a surface 141 and at least one opening 142. The opening 142 exposes the first end 131 of the through via 13. The redistribution layer 15 is disposed on the surface 141 and the opening 142 of the passivation layer 14, and the redistribution layer 15 has at least one electrically connecting area 151, and the electrically connecting area 151 connects the first end 131 of the through via 13.
The conventional silicon chip 1 having a through via has the following disadvantages. The diameter D1 of the opening 142 of the passivation layer 14 must be smaller than the diameter D2 of the through hole 113 of the silicon substrate 11, or the electrically connecting area 151 of the redistribution layer 15 will directly contact the silicon substrate 11, which will lead to a short circuit. However, the passivation layer 14 is generally patterned by an exposing and developing process, and the resolution of the process is low, so accurate and precise patterns cannot be manufactured. Therefore, the diameter D1 of the opening 142 of the passivation layer 14 is likely to be greater than the diameter D2 of the through hole 113 of the silicon substrate 11, and the electrically connecting area 151 of the redistribution layer 15 will directly contact the silicon substrate 11, which will lead to a short circuit. On the other hand, if the passivation layer 14 is patterned by a high resolution process, more subsequent processes are needed, so the method will become complex and costly.
Therefore, it is necessary to provide a silicon chip having a through via and a method for making the same to solve the above problems.